1. Technical Field
The disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device. More particularly, example embodiments relate to a semiconductor device including a self-aligned contact pad and a method of manufacturing the semiconductor device including the self-aligned contact pad.
2. Description of the Related Art
As semiconductor devices have become highly integrated, widths of patterns and intervals between the patterns have become decreased in the semiconductor devices. Thus, as a width of a pattern (i.e., design rule) decreases, a length of a channel region in a metal-oxide semiconductor (MOS) transistor is shortened. When the channel is shorter than an effective length required for an operation of the MOS transistor, a short channel effect may occur at the channel of the MOS transistor, to thereby deteriorate electrical characteristics of the MOS transistor. Therefore, the MOS transistor requires a gate structure having a sufficient channel length to minimize short channel effects.
To prevent the short channel effect and to improve operation performance of the MOS transistor, a recessed channel has been developed and a transistor including the recessed channel is now under mass production. For example, U.S. Patent Application Publication No. 2005-0014338 discloses a semiconductor device including the recessed channel and a method of manufacturing the same.
The above recessed channel gives a sufficiently satisfying solution to problems due to a short effective length of the channel. However, the recessed channel also causes various processing problems due to a high ratio of a height with respect to a width of a gate. FIG. 1 is a cross-sectional view illustrating a conventional semiconductor device including a recessed channel.
Referring to FIG. 1, a conventional semiconductor device includes a substrate 10, a gate insulation layer 16, a gate structure 17 and a spacer 24.
The substrate 10 includes an isolation layer 12 and a recess portion 14. The gate insulation layer 16 is continuously formed on the recess portion 14 of the substrate 10. The gate structure 17 includes a first gate pattern 18, a second gate pattern 20 and a mask pattern 22 for forming the first and the second gate patterns. The first and the second gate patterns 18 and 20, which are sequentially formed on the gate insulation layer 16, may serve as a word line of the semiconductor device. For example, the first gate pattern 18 comprises doped polysilicon, and the second gate pattern 20 comprises tungsten silicide. The mask pattern comprises a nitride such as silicon nitride and silicon oxynitride. The spacer 24 is positioned on a sidewall of the gate structure 17. The spacer 24 may protect the first and the second gate patterns 18 and 20 in a subsequent self-aligned contact (SAC) process.
A conductive pattern 30 is formed on the gate insulation layer 16 between the gate structures adjacent to each other through the SAC process, so that the width of the gate structure 17 becomes very small. For that reason, an aspect ratio, which is the ratio of a height with respect to a width of the gate structure 17, becomes very high in the conventional semiconductor device. Particularly, an insulating interlayer 26 is formed on a resultant structure including the gate structure 17 to a sufficient thickness to cover the gate structures 17, and the insulating interlayer 26 is partially etched from the resultant structure to form an opening 28 through which an impurity region (not shown) is exposed. Since the opening 28 is formed through an anisotropic etching process against the insulating interlayer 26 having an etching selectivity with respect to the mask pattern 26 and the spacer 24, damage is easily caused to the first and second gate patterns 18 and 20 in the anisotropic etching process. Therefore, the mask pattern 22 requires a great thickness substantially identical to an overall height of the first and the second gate patterns 18 and 20 for prevention of the damage to the first and the second gate patterns 18 and 20 in the above etching process. As a result, the mask pattern 24 is necessarily formed to be high and a width of the gate structure 17 tends to be small due to a high integration degree, so that the aspect ratio of the gate structure 17 necessarily becomes high.
However, the opening 28 through which the impurity region of the substrate 10 is exposed is difficult to form in the insulating interlayer 26 due to the high aspect ratio of the gate structure 17. Furthermore, a shoulder portion, or a top edge portion, of the gate structure 17 becomes so weak from a structural viewpoint due to the high aspect ratio, that an electrical short circuit is generated between the first and second gate patterns 18 and 20 and a conductive pattern 30 in the opening 28. What is worse, the gate structure 17 may be broken due to stress at an interface between the second gate pattern 20 comprising tungsten silicide and the mask pattern 22.
In addition, the spacer usually comprises a dielectric material having a relatively high dielectric constant, such as silicon nitride, so as to facilitate the SAC process. However, there is a problem in that the dielectric material having a relatively high dielectric constant generates a large parasitic capacitance around the word line as a width of the word line becomes small.